Over the past twenty-five years or so, the primary challenge of very large scale integration (VLSI) has been the integration of an ever-increasing number of metal oxide semiconductor field effect transistor (MOSFET) devices with high yield and reliability. This was achieved mainly in the prior art by scaling down the MOSFET channel length without excessive short-channel effects. As is known to those skilled in the art, short-channel effects are the decrease of threshold voltage Vt in short-channel devices due to two-dimensional electrostatic charge sharing between the gate and the source/drain diffusion regions.
To scale down MOSFET channel lengths without excessive short-channel effects, gate oxide thickness has to be reduced while increasing channel-doping concentration. However, Yan, et al., “Scaling the Si MOSFET: From bulk to SOI to bulk”, IEEE Trans. Elect. Dev., Vol. 39, p. 1704, Jul. 1992, have shown that to reduce short-channel effects for sub-0.05 μm MOSFETs, it is important to have a backside-conducting layer present in the structure that screens the drain field away from the channel. The Yan, et al. results show that double-gated MOSFETs and MOSFETs with a top gate and a backside ground plane are more immune to short-channel effects and hence can be scaled to shorter dimensions than conventional MOSFETs.
The structure of a typical prior art double-gated MOSFET consists of a very thin vertical semiconductor layer (Fin) for the channel, with two gates, one on each side of the channel. The term “Fin” is used herein to denote a semiconducting material which is employed as the body of the FET. The two gates are electrically connected so that they serve to modulate the channel. Short-channel effects are greatly suppressed in such a structure because the two gates very effectively terminate the drain field line preventing the drain potential from being felt at the source end of the channel. Consequently, the variation of the threshold voltage with drain voltage and with gate length of a prior art double-gated MOSFET is much smaller than that of a conventional single-gated structure of the same channel length.
In the semiconductor industry, semiconductor Fins can be processed either by optical or ebeam lithographic processes in combination with trimming processes such as, for example, resist trimming, hard mask trimming or oxidation trimming. Another method of trimming is by utilizing a sidewall image transfer (SIT) process. The SIT process provides very high-density structures that are independent of lithographic resolution and pitch. The SIT process is based upon a spacer that is formed on the sidewall of an optical defined structure. The spacer is used as a mask to define the structure of the underlying layer or layers.
In conventional FinFET fabrication processes two etching steps are used (one during the lithographic step and another during trimming) which greatly decreases the possibility of forming FinFETs having controlled gate widths.
In view of the above, there is a need for providing a new and improved method of fabricating FinFETs wherein improved gate width control is provided that eliminates the need for utilizing a combination of optical or ebeam lithography and trimming.